The present invention relates to asynchronous counter circuits, analog-to-digital (AD) conversion methods and AD converters for converting analog signals into digital data using the counter circuits, semiconductor devices for detecting distribution of physical quantities by an array of a plurality of unit elements, and electronic apparatuses.
More specifically, the present invention relates to an asynchronous counter and techniques of AD conversion, suitably used in electronic apparatuses, for example, a semiconductor device for detecting distribution of physical quantities, such as a solid-state imaging device, that allows reading electric signals representing distribution of physical quantities obtained by an array of a plurality of unit elements that are sensitive to electromagnetic waves input from the outside, such as light or radiation.
Semiconductor devices for detecting physical quantities, including a line or matrix of unit elements that are sensitive to electromagnetic waves input from the outside, such as light or radiation, are used in various fields.
For example, in the field of video apparatuses, charge coupled device (CCD), metal oxide semiconductor (MOS), and complementary metal oxide semiconductor (CMOS) solid-state imaging devices for detecting light (an example of electromagnetic wave) as a physical quantity are used. These devices read distribution of physical quantities in the form of electric signals obtained by unit elements (pixels in the case of a solid-state imaging device).
In a type of solid-state imaging device, referred to as an active pixel sensor (APS) or gain cell, a driving transistor for amplification is provided in a pixel signal generator that generates a pixel signal corresponding to signal charges generated by a charge generator. Many CMOS solid-state imaging devices are of the type described above.
In such an active pixel sensor, in order to read pixel signals to the outside, address control is exercised on a pixel unit including an array of unit pixels so that signals can be read from arbitrarily selected individual unit pixels. That is, an active pixel sensor is an example of address-controlled solid-state imaging device.
For example, in an active pixel sensor, which is a type of X-Y-addressed solid-state imaging device including a matrix of unit pixels, each pixel is implemented using an active element of the MOS structure (MOS transistor) or the like so that the pixel itself is capable of amplification. That is, signal charges (photoelectrons) accumulated in a photodiode that functions as a photoelectric converter are amplified by the active element, and the amplified signals are read as image information.
In this type of X-Y-addressed solid-state imaging device, for example, a pixel unit includes a two-dimensional array of a large number of pixel transistors. Accumulation of signal charges corresponding to incident line is started on a line-by-line basis or pixel-by-pixel basis. Current or voltage signals based on the accumulated signal charges are sequentially read from the respective pixels according to addressing. In the case of MOS (including CMOS) solid-state imaging device, as an example of address control, according to a method that is often used, pixels on one row are simultaneously accessed to read pixel signals from the pixel unit on a row-by-row basis.
The analog pixel signals read from the pixel unit are converted into digital data by an analog-to-digital converter as needed. Since the pixel signals are output with signal components added to reset components, true effective signal components must be extracted by taking difference between signal voltage corresponding to reset component and signal voltage corresponding to signal component.
This also applies to a case where analog pixel signals are converted into digital data. Ultimately, a difference signal component representing a difference between a signal voltage corresponding to a reset component and a signal voltage corresponding to a signal component must be converted into digital data. For this purpose, various schemes for AD conversion have been proposed, for example, as described in W. Yang et. al., “An Integrated 800×600 CMOS Image System,” ISSCC Digest of Technical Papers, pp. 304-305, February 1999 (hereinafter referred to as a first non-patent document), YONEMOTO Kazuya, “CCD/CMOS Imeeji sensa no kiso to ouyou”, CQ Publishing Co., Ltd., Aug. 10, 2003, First Edition, pp. 201 to 203 (hereinafter referred to as a second non-patent document), IMAMURA Toshifumi and YAMAMOTO Yoshiko, “3. Kousoku kinou CMOS imeeji sensa no kenkyuu”, found on the Internet on Mar. 15, 2004 at an URL
http://www.sanken.gr.jp/project/iwataPJ/report/h12/h12index.html (hereinafter referred to as a third non-patent document), IMAMURA Toshifumi, YAMAMOTO Yoshiko, and HASEGAWA Naoya, “3. Kousoku kinou CMOS imeeji sensa no kenkyuu”, found on the Internet on Mar. 15, 2004 at an URLhttp://www.sanken.gr.jp/project/iwataPJ/report/h14/h14index.html (hereinafter referred to as a fourth non-patent document), Oh-Bong Kwon et. al., “A Novel Double Slope Analog-to-Digital Converter for a High-Quality 640×480 CMOS Imaging System”, VL3-03, 1999, IEEE, pp. 335 to 338 (hereinafter referred to as a fifth non-patent document), and Japanese Unexamined Patent Application Publication No. 11-331883 (hereinafter referred to as a first patent document).
According to the schemes of AD conversion described in the first to fifth non-patent documents and the first patent document, AD conversion is performed using a counter circuit. The counter circuit used is usually a synchronous counter in which a flip-flop (basic element of the counter) outputs a count value in synchronization with a counter clock.
In the case of a synchronous counter, however, the operations of all the flip-flops are restricted by the count clock, which is problematic when an operation at a higher frequency is needed.
It is also possible to use an asynchronous counter as a counter circuit, as described, for example, in the fourth and fifth non-patent documents. An asynchronous counter is suitable for high-speed operation since the limiting operation frequency thereof is determined only by the limiting frequency of the first flip-flop. Thus, an asynchronous counter is preferably used as a counter circuit when an operation at a higher frequency is needed.
FIG. 18 is a diagram showing an asynchronous counter according to the related art, which is capable of switching mode. A counter circuit 900 is capable of functioning as a 4-bit asynchronous counter. For example, the counter circuit 900 is implemented by cascade connection of a plurality of negative-edge D flip-flops 912, 914, 916, and 918 (collectively 910). Each of the flip-flops 910 has an inverting output NQ (indicated with a horizontal bar over Q) connected to a D input terminal thereof. A clock terminal CK of the first flip-flop 910 receives input of a count clock CK0.
Furthermore, the counter circuit 900 includes two-input single-output switches 922, 924, and 926 (collectively 920) for switching the values of the non-inverting outputs Q and the inverting outputs NQ of the flip-flops 910 respectively between the adjacent pairs of the flip-flops 910. Each of the switches 920 switches the two input signals according to a control signal SW from a controller (not shown) and inputs a selected signal to the clock terminal CK of the subsequent flip-flop 910.
The control signal SW is used to switch counting operation of the counter circuit 900 between up-counting and down-counting. When the control signal is at High (H) level, the non-inverting output Q is selected so that the counter circuit 900 enters an up-count mode. On the other hand, when the control signal SW is at Low (L) level, the inverting output NQ is selected so that the counter circuit 900 enters a down-count mode.
In the conventional asynchronous counter shown in FIG. 18, however, counting is performed commonly using an up/down counter irrespective of operation mode while switching processing mode of the up/down counter. Thus, although compact design of the circuit is allowed, for example, when the counter counts up to a predetermined value ad then starts counting down from the value, the continuity of count value is not maintained in at the time of switching of count mode. Thus, the counter is not suitable for performing counting continuously while switching count mode (hereinafter referred to as a first problem). This will be described below.
FIG. 19 is a timing chart for explaining the operation of the counter circuit 900 shown in FIG. 18.
In this example, a 4-bit asynchronous counter switches between the non-inverting output Q and the inverting output NQ according to the control signal SW, so that up-counting is first performed and then down-counting is performed. When switching from up-counting to down-counting occurs, however, the count value changes from 6 to 10. Thus, it is not possible to perform up-counting and down-counting while maintaining the count value before and after switching of count mode using a pulse train having a high frequency.
A scheme for overcoming this problem is proposed, for example, in Japanese Unexamined Patent Application Publication No. 6-216762 (hereinafter referred to as a second patent document). According to the second patent document, a device for inverting the status of each flip-flop and a device for initializing all the flip-flops on each even-numbered pulse train are provided.
The method of counting described in the second patent document will be described below. It is assumed that an asynchronous counter is capable of counting up to a maximum number n, a first pulse train includes i pulses, and a second pulse train includes j pulses.
The counter is reset in advance, and counts from 0 to i for the first pulse train. Then, when the status of the flip-flops of the counter is inverted, the n's complement of the value i is obtained, so that the value of the counter becomes n−i.
The counter then counts from n−i to n−i+j. The difference of interest i−j is the n's complement of n−i+j, which is obtained by inverting the status of the flip-flops again. Thus, an asynchronous counter for performing up-counting and down-counting using a continuous pulse train having a high frequency is implemented.
According to the scheme described in the second patent document, however, since up-counting and down-counting are performed by calculation involving complement values, which is not direct (hereinafter referred to as a second problem).
Furthermore, the schemes of AD conversion described in the first to fifth non-patent documents and the first patent document have drawbacks relating to circuitry scale, circuit area, power consumption, the number of wires for interfacing with other functional units, noise associated with the wires, or consumption current. This will be described below.
Construction of Solid-State Imaging Device According to the Related Art
FIG. 21 is a schematic construction diagram of a CMOS solid-state imaging device (CMOS image sensor) according to the related art, in which an AD converter and a pixel unit are mounted on the same semiconductor substrate. As shown in FIG. 21, a solid-state imaging device 1 includes a pixel unit (imaging unit) 10 in which a plurality of unit pixels 3 is arranged in rows and columns, a driving controller 7 provided externally to the pixel unit 10, a counter (CNT) 24, a column processor 26 including column AD circuits 25 provided for the respective columns, a reference-signal generator 27 including a digital-to-analog converter (DAC) for supplying a reference voltage for AD conversion to the column AD circuits 25 in the column processor 26, and an output circuit 28 including a subtractor circuit 29.
The driving controller 7 includes a horizontal scanning circuit (column scanning circuit) 12 that controls column address or column scanning, a vertical scanning circuit (row scanning circuit) 14 that controls row address or row scanning, and a timing controller 21 that receives a master clock CLK0 via a terminal 5a and that generates various internal clocks to control the horizontal scanning circuit 12, the vertical scanning circuit 14, and the like.
The unit pixels 3 are connected to row control lines 15 that are controlled by the vertical scanning circuit 14 and to vertical signal lines 19 that transfer pixel signals to the column processor 26.
Each of the column AD circuits 25 includes a voltage comparator 252 and a data storage unit (latch) 255, and it has a function of an n-bit AD converter. The voltage comparator 252 compares a reference signal RAMP generated by the reference-signal generator 27 with an analog signal obtained for each row control line 15 (H0, H1, . . . ) from the unit pixels 3 via the vertical control lines 19 (V0, V1, . . . ). The data storage unit 255 is a memory that holds a result of counting a time taken by the voltage comparator 252 to finish comparison by the counter 24. The data storage unit 255 includes n-bit latches 1 and 2 that are storage areas independent of each other.
One input terminal RAMP of the voltage comparator 252 receives input of a stairs-like reference signal RAMP generated by the reference-signal generator 27 commonly with the input terminals RAMP of the other voltage comparators 252. The other input terminals of the voltage comparators 252 are connected to the vertical signal lines of the respectively associated columns so that pixel signals from the pixel unit 10 are individually input. Signals output from the voltage comparators 252 are supplied to the data storage units 255. The reference signal RAMP is digitally generated by performing counting based on a count clock CK0 corresponding to the master clock CLK0 (e.g., clock frequencies of these clocks are equal) supplied from the outside of the solid-state imaging device 1 and converting the count value into an analog signal.
The counter 24 performs counting based on the count clock CK0 that is based on the master clock CLK0 (e.g., clock frequencies of these clocks are the same), and supplies count outputs CK1, CK2, . . . , CKn, together with the count clock CK0, commonly to the column AD circuits 25 of the column processor 26.
That is, by providing lines for the count outputs CK1, CK2, . . . , CKn from the counter 24 to the latches of the data storage units 255 provided for the respective columns, the column AD circuits 25 for the respective columns share the single counter 24.
The outputs of the column AD circuits 25 are connected to horizontal signal lines 18. The horizontal signal lines 18 have signal lines for 2n bits, and are connected to the subtractor circuit 29 of the output circuit 28 via 2n sensing circuits (not shown) associated with the respective output lines.
The timing controller 21 instructs, via a control line 12c, the horizontal scanning circuit 12 to read pixel data. In response to the instruction, the horizontal scanning circuit 12 sequentially transfers pixel data held in the latches 1 and 2 to the subtractor circuit 29 of the output circuit 28 by sequentially shifting a horizontal select signal CH(i). That is, the horizontal scanning circuit 12 performs read scanning in the horizontal (row) direction.
The horizontal scanning circuit 12 generates a horizontal select signal CH(i) for performing read scanning in the horizontal (row) direction based on the master clock CLK0 supplied from the outside of the solid-state imaging device 1, similarly to the count clock CK0.
FIG. 22 is a timing chart for explaining an operation of the solid-state imaging unit 1 according to the related art shown in FIG. 21.
For example, for the first reading operation, the count value of the counter 254 is first reset to an initial value “0”. Then, after the first reading operation of reading pixel signals from unit pixels 3 on an arbitrary row Hx to the vertical signal lines 19 (V0, V1, . . . ) becomes stable, a reference signal RAMP generated by the reference-signal generator 27, temporally changing so as to form substantially ramp waveform, is input, which is compared by the voltage comparator 252 with a pixel signal voltage on an arbitrary vertical signal line 19 (with a column number Vx).
At this time, simultaneously with the input of the reference signal RAMP to the one input terminal RAMP of the voltage comparator 252, in order to measure a comparison time of the voltage comparator 252 by the counter 24, in synchronization with the ramp waveform voltage generated by the reference-signal generator 27 (t10), the counter 24 starts down-counting from the initial value “0” as the first counting operation.
The voltage comparator 252 compares the ram reference signal RAMP from the reference-signal generator 27 with a pixel signal voltage Vx input via a vertical signal line 19. When these voltages become equal, the voltage comparator 252 inverts its output from H level to L level (t12).
Substantially at the same time with the inversion of the output of the voltage comparator 252, the data storage unit 255 latches the count outputs CK1, CK2, . . . CKn from the counter 24 in accordance with a comparison period in the latch 1 of the data storage unit 255 in synchronization with the count clock CK0, whereby the first iteration of AD conversion is completed (t12).
When a predetermined down-count period elapses (t14), the timing controller 21 stops supply of control data to the voltage comparator 252 and supply of the count clock CK0 to the counter 254. Thus, the voltage comparator 252 stops generating the ramp reference signal RAMP.
In the first reading operation, reset components Δ of the unit pixels 3 are read, and the reset components Δ includes offset noise that varies among the unit pixels 3. Generally, however, the variation in the reset components Δ is small, and the reset levels are common among all the pixels, so that the output of an arbitrary vertical signal line 19 (Vx) is substantially known.
Thus, when the reset components Δ are read in the first reading operation, it is possible to shorten the comparison period by adjusting the reference signal RAMP. According to this related art, the reset components Δ are compared in a count period corresponding to 7 bits (128 clock cycles).
In the second reading operation, in addition to the reset components Δ, signal components Vsig corresponding to the amounts of light incident on the respective unit pixels 3 are read, and the operation similar to the first operation is performed.
More specifically, for the second reading operation, the count value of the counter 254 is first reset to the initial value “0”. Then, when the second reading operation of reading pixel signals from the unit pixels 3 on an arbitrary row Hx to the vertical signal lines 19 (V0, V1, . . . becomes stable, a reference signal RAMP generated by the reference-signal generator 27 so as to temporally change in a stairs-like manner and have substantially ramp waveform is input, and the voltage comparator 252 compares the reference signal RAMP with a pixel signal voltage on an arbitrary vertical signal line 19 (with a column number Vx).
At this time, simultaneously with the input of the reference signal RAMP to the one input terminal RAMP of the voltage comparator 252, in order to measure a comparison time of the voltage comparator 252 using the counter 24, in synchronization with the ramp waveform voltage generated by the reference-signal generator 27 (t20), the counter 24 starts down-counting from the initial value “0” as the second counting operation.
The voltage comparator 252 compares the ramp reference signal RAMP from the reference-signal generator 27 with a pixel signal voltage Vx input via a vertical signal line 19. When these voltages become equal, the voltage comparator 252 inverts its output from H level to L level (t22).
Substantially at the same time as the inversion of the output of the voltage comparator 252, the data storage unit 255 latches the count outputs CK1, CK2, . . . , CKn from the counter 24 in accordance with the comparison period in synchronization with the count clock CK0, whereby the second iteration of AD conversion is completed (t22).
At this time, the data storage unit 255 holds the count value in the first counting operation and the count value in the second counting operation in different places thereof, namely, in the latch 2. In the second reading operation, combinations of the reset components A and the signal components Vsig of the unit pixels 3 are read.
When a predetermined down-count period elapses (t24), the timing controller 21 stops supply of control data to the voltage controller 252 and supply of the count clock CK0 to the counter 254. Thus, the voltage comparator 252 stops generating the ramp reference signal RAMP.
At specific timing (t28) after the second counting operation is completed, the timing controller 21 instructs the horizontal scanning circuit 12 to read pixel data. In response to the instruction, the horizontal scanning circuit 12 sequentially shifts the horizontal select signal CH(i) supplied to the data storage unit 255 via the control line 12c. 
Thus, the count value latched in the data storage unit, i.e., pixel data in the first iteration and the second iteration each represented by n-bit digital data is sequentially output to the outside of the column processor 26 via n (2n in total) horizontal signal lines 18 and is input to the subtractor circuit 29 of the output circuit 28.
The n-bit subtractor circuit 29, for each pixel position, subtracts the pixel data of the first iteration, representing the reset component Δ of a unit pixel 3, from the pixel data of the second iteration, representing the combination of the reset component Δ and the signal component Vsig of the unit pixel 3, calculating the signal component Vsig of the unit pixel 3.
Then, similar operation is sequentially performed on a row-by-row basis, whereby image signals representing a two-dimensional image are obtained in the output circuit 28.
However, in the arrangement shown in FIG. 21, the column AD circuits of the respective columns shares the single counter 24, and the results of the first and second counting operations must be held in the data storage unit 255 that functions as a memory. Thus, two n-bit latches are needed for an n-bit signal (2n latches are needed for each bit), causing an increase in circuit area (hereinafter referred to as a third problem).
Furthermore, lines for inputting the count clock CK0 and n count outputs CK1, CK2, . . . , CKn from the counter 24 to the data storage unit 255 are needed. This could increase noise or power consumption (hereinafter referred to as a fourth problem).
Furthermore, in order to hold count values of the first and second counting operations at different locations of the data storage unit 255, 2n signal lines for transmitting the results of the first and second counting operations are needed, which causes an increase in the amount of current (hereinafter referred to as a fifth problem).
Furthermore, before a signal is output to the outside of the device, in order to subtract the count value of the first counting operation from the count value of the second counting operation, 2n signal lines for leading the count values to the n-bit subtractor circuit 29 of the output circuit 28 are needed. This could increase noise or power consumption for transferring data (hereinafter referred to as a sixth problem).
That is, a memory for holding the result of the first reading operation and a memory for holding the result of the second reading operation must be individually provided (i.e., two memories are needed) separately from the counter. Furthermore, signal lines for transmitting n-bit count values from the memories to the counter are needed. Furthermore, in order to transfer the n-bit count values of the first and second counting operations to the subtractor, signal for 2n bits (double) are needed. This increases circuitry scale and circuit area, and also increases noise, consumption current, or power consumption.
Furthermore, when AD conversion and reading operation are executed in parallel, i.e., by a pipeline operation, a memory for holding data obtained by AD conversion is needed separately from a memory for holding the result of counting. Similarly to the third problem, two memories are needed for this purpose, causing an increase in circuit area (hereinafter referred to as a seventh problem).
As a measure for overcoming the third problem, in a proposed column AD converter circuit, a correlated double sampling (CDS) function and an AD conversion function are implemented by providing in series a counter that is commonly used among columns, and a CDS processing unit and a latch for holding the count value of the counter, provided for each column. This is described, for example, in the second non-patent document.
Furthermore, in a proposed scheme for overcoming the second problem, for example, an AD conversion function is implemented by providing a counter for each column in the column processor 26. This is described, for example, in the third and fourth non-patent documents.
In a column AD circuit described in the second non-patent document, AD converters including counters and latches, which perform parallel processing for the vertical signal lines (columns), converts analog signals into digital signals by taking the difference between a reset component and a signal component while suppressing fixed pattern noise of pixels. Thus, subtraction is not needed, and a single counting operation suffices. Furthermore, memories for holding data obtained by AD conversion can be implemented by latches. This serves to avoid increase in circuit area. That is, the third, fifth, sixth, and seventh problems are overcome.
However, lines for inputting the count clock CK0 and n count outputs from the counters to the latches are needed, so that the fourth problem is not overcome.
According to techniques described in the third and fourth non-patent documents, currents from a plurality of pixels that detect light are simultaneously output onto an output bus, and addition and subtraction are performed in terms of currents on the output bus. Then, signals are converted into pulse-width signals having magnitudes in the temporal direction, and the clock cycles of the pulse widths of the pulse-width signals are counted by counter circuits provided for the respective columns, thereby performing AD conversion. Accordingly, wires for count outputs are not needed, i.e., the fourth problem is overcome.
However, handing of a reset component and a signal component is not described, so that the third, fifth, sixth, and seventh problems are not necessarily overcome. Handling of a reset component and a signal component is not described either in the first and fifth non-patent documents.
On the other hand, the first patent document describes handling of a reset component and a signal component. In order to extract voltage data of a pure image from a reset component and a signal component, for example, by correlated double sampling, digital data of the reset component is subtracted from digital data of the signal component for each column, so that the sixth problem is avoided.
However, according to techniques described in the first patent document, counting is performed in an external system interface to generate a count signal, and a count value at a time when a voltage of the reset component or the signal component matches a reference voltage for comparison is saved in a pair of buffers provided for each column. Thus, the scheme of AD conversion is the same as that in the first non-patent document in that a single counter is commonly used by the columns. Thus, the third to fifth and seventh problems cannot be avoided.